The present invention is directed to integrated circuits and their operation. More particularly, the invention provides a method and system for enhanced data read performance in an integrated circuit. Merely by way of example, the invention has been applied to serial memory devices incorporating a serial peripheral interface protocol for fast data transfer rate. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to integrated circuits including other stand-alone or embedded memory devices such as DRAM, SRAM, parallel flash, or other non-volatile memories. The present invention can also be applied to a serial peripheral interface for use in communication between electronic devices.
Flash memories are used in a variety of applications in electronics. These memory devices often include a large number of input and output pins to accommodate data and addresses required to access the memory cells. In response to increasing space and wiring demands, serial flash memories have been developed to provide reduced pin counts, often requiring only one or two data pins. These serial flash memories provide a storage solution for systems with limited space, pin connections, and power supplies. Serial flash memories can be used for code download applications, as well as for storage of voice, video, text, and data, etc. However, conventional serial flash memory devices have many limitations. For example, a conventional serial peripheral interface flash memory device transfers data or address bits in a sequential and serial fashion, limiting the speed of the memory device.
From the above, it is seen that an improved technique for serial peripheral interface is desired.